1. Field of the Invention
This invention relates to a semiconductor memory. More particularly, it relates to a nonvolatile semiconductor memory in which the amount of electric charge controlled by injecting or releasing electric charge in or from a gate insulating film can be retained for a relatively long time even after turn-off of a controlling means, thus having nonvolatile memory effect.
2. Description of the Prior Art
FIG. 8A illustrates an example of a prior art nonvolatile MIS transistor (Japanese Laid-open Patent Application No. 47-6921 of Apr. 15, 1972). An about 3 nm thick SiO.sub.2 film 2 that enables injection and release of electric charge, attributable to tunnel effect, is formed at the top surface of a semiconductor substrate 1, and a plurality of particles 3 with a size of about 3 nm which are scatteringly provided so as to undergo no mutual action (comprising, for example, a semiconductor or a metallic material, specifically including refractory metals such as Mo, and noble metals such as Pt and Ag) are formed by vacuum deposition or the like. Next, an SiO.sub.2 film, Si.sub.3 N.sub.4 film or Al.sub.2 O.sub.3 film 5 with a thickness of as relatively large as about 75 nm is formed by CVD or the like. The numeral 6 denotes a gate electrode, and 8, a source region or a drain region. The numeral 7 denotes metallic wiring that forms an ohmic contact between the source regions or drain regions, and 9, a substrate contact to the semiconductor substrate 1. As an example in which the insulating films 2 and 5 are formed into a single layer film using the same material, the above Japanese Laid-open Patent Application No. 47-6921 discloses an instance in which metal or semiconductor ions (In.sup.+ and Nb.sup.+ are exemplified as suitable ion species) are shot into the interior by ion implantation. This Japanese Laid-open Patent Application No. 47-6921 discloses an example of measurement for an actual nonvolatile memory effect as shown in FIG. 8B. In FIG. 8B, the capacity ratio C/C.sub.O, standardized to the capacity C.sub.O of an insulating film, is indicated as a function of an applied voltage on the gate electrode 6. This actual measurement example is concerned with a gate electrode with two-layer structure comprised of a 25 nm thick SiO.sub.2 film 2 and a 75 nm thick Al.sub.2 O.sub.3 film 5, where the particles 3 comprise Pt particles with a nominal size of 3.5 nm, formed by vacuum deposition, when the particles 3 are present, a great hysteresis effect is observed as shown by solid lines. On the other hand, when no particles are present, little hysteresis effect is observed as shown in dotted lines. There, however, is no disclosure as to any example of actual measurement for an instance in which the particles are formed by ion implantation, and it can not be conjectured that a test sample has been prepared. Even if It is conceived that the In.sup.+ or Nb.sup.+ ions exemplified in Japanese Laid-open Patent Application No. 47-6921 are implanted in the vicinity of the interface between the insulating films, it is presumed that the implanted ions go through the insulating film and are implanted in the Si substrate, so that the In.sup.+ or Nb.sup.+ ions behave as impurities of Group III or Group V ions, respectively, and a great change is caused in the threshold voltage of the MIS transistor.
More specifically, as in the prior art, ions are implanted under Gaussian distribution in order to implant ions so as to have a peak density in the vicinity of about 3 nm from the Si substrate and to give an amount of implantation of approximately from 10.sup.16 to 10.sup.17 cm.sup.-2, so that ions go through an insulating film of about 3 nm thick and implanted in the Si substrate in a dose of approximately from 10.sup.14 to 10.sup.16 cm.sup.-2. Thus, the implantation of a large quantity of Group III or Group V impurities in the Si substrate is presumed to cause a very great change in the threshold voltage, which is as great as several volts or more, thus making it impossible to control the threshold voltage (approximately from 0.5 V to 1.0 V in usual instances) of the MIS transistor. In other words, since the dose of the impurities of Group III or Group V ions, used for controlling of the threshold voltage Of the MIS transistor is approximately from 10.sup.12 to 10.sup.13 cm.sup.-2. it therefore becomes impossible to control the threshold voltage when the In.sup.+ or Nb.sup.+ ions are in a larger dose by the factor of one figure to three figures
Moreover, even if it is attempted to form the peak of ion implantation impurity distribution at the position of about 3 nm from the Si substrate, the non-uniformity of dose of the In.sup.+ or Nb.sup.+ ions implanted in the Si substrate is very great when the non-uniformity of the gate electrode or ion implantation energy is taken into account, and also the change in the threshold voltage, caused by In.sup.' or Nb.sup.+ ions, is great. Thus, it becomes impossible to control the threshold voltage of the MIS transistor.
As discussed in the above, the method of forming the particles 3 by the ion implantation conceivable from the prior art can not control the threshold voltage of the MIS transistor, and hence can not be worked as a method of providing a nonvolatile semiconductor memory.